new NanoStack has allowed researchers to integrate up to 100 billion transistors onto a single chip, offering 50% higher performance and 70% lower power consumption compared to today's generation of semiconductors.
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For the first time, scientists have managed to build transistors with dimensions smaller than 1 nanometer (nm). According to the research team, the NanoStack architecture could in the future even lead to the development of transistors as small as 0.1 nm.
The new 0.7nm are significantly smaller than those used in today's 2nm, which power supercomputers, artificial intelligence applications, and advanced graphics processing units (GPUs). While the name of a manufacturing node (such as 2nm) does not necessarily correspond to the exact physical dimensions of the transistors, it is an indication of the overall capabilities and density of the chip.
The smaller the transistors and other components of an integrated circuit, the more they can fit on the same surface area. A typical 2nm chip can accommodate about 50 billion transistors in a space about the size of a human fingernail.
In the new design, transistors are so tiny that their dimensions are now expressed in ångström (Å) – a unit of measurement used primarily to describe atomic distances. The first chips using this technology are expected to use transistors that are 7 Å, or 0.7 nanometers, about the width of a glucose molecule.
Thanks to this extremely high integration density, engineers can fit nearly 100 billion transistors onto a surface the size of a fingernail, almost double the number of transistors on today's 2nm platform.
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The researchers achieved this technological leap by utilizing a new method, known as NanoStack, which they initially presented in a study published at the Symposium on VLSI Technology and Circuits 2025 and posted in July 2025 on the IEEE Xplore.
This technique allows for the vertical stacking of nanosheets used in the manufacture of previous-generation 2 nm, significantly increasing transistor density without requiring a larger silicon surface area.
Conventional integrated circuit manufacturing technology, known as CMOS (Complementary Metal-Oxide-Semiconductor), requires extremely high temperatures during the manufacturing process. However, as transistors become smaller, increasingly serious technical challenges arise. These include charge trapping, in which electrons or holes become trapped due to defects or impurities in the material, and gate leakage, a phenomenon that causes unwanted static electricity consumption and reduces the energy efficiency of circuits.
According to the researchers, IBM's new 3D NanoStack architecture is designed to address several key issues that arise as transistors continue to shrink. The vertical stacking technology enables higher integration density, improved performance and lower power consumption, without the limitations of conventional manufacturing methods.
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IBM said the new technology offers up to 50 percent higher performancewhile reducing power consumption by 70 percent compared to the current 2-nanometer (2 nm). The company estimates that this architecture is expected to completely replace current technology within the next five years, forming the basis for the next generation of integrated circuits.
